`timescale 1ns / 1ps 
/**
 ******************************************************************************
 * @file    clk_div.v
 * @author  KEN
 * @version V1.1
 * @date    May. 12nd, 2020
 * @brief   Clock divide Module
 ******************************************************************************
 * @attention
 *
 * <h2><center>&copy; COPYRIGHT 2020 K'sP</center></h2>
 ******************************************************************************
 */

module clk_div
	   #
	   (
		   parameter C_FREQ_WORD_WIDTH = 32
	   )
	   (
		   input wire aclk,
		   input wire aresetn,

		   input wire [(C_FREQ_WORD_WIDTH - 1): 0] FREQ_WORD,

		   output wire clk_out
	   );

reg clk_out_r;
reg [(C_FREQ_WORD_WIDTH - 1): 0] max_value;

assign clk_out = clk_out_r;

always@(posedge aclk or negedge aresetn)
begin
	if (~aresetn)
	begin
		max_value <= 1'b0;
	end
	else
	begin
		max_value <= max_value + FREQ_WORD;
	end
end

always@(posedge aclk or negedge aresetn)
begin
	if (~aresetn)
	begin
		clk_out_r <= 1'b0;
	end
	else
	begin
		clk_out_r <= (max_value < ((1 << (C_FREQ_WORD_WIDTH - 1)) - 1)) ? 1'b0 : 1'b1;
	end
end

endmodule